1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to the fabrication of a metal silicide with silicon barrier characteristics.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon to form an integrated circuit. The entire process of making an ohmic contact to the contact areas and routing interconnect material between ohmic contacts is described generally as "metallization". While materials other than metals are often used, the term metallization is generic in its application and is derived from the origins of interconnect technology, where metals were the first conductors used. As the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased.
In order to form highly conductive ohmic contacts in the connecting region or "window{38 between the interconnects (generally aluminum), it is oftentimes necessary to incorporate a layer of refractory metal at the juncture. The refractory metal, when subjected to high enough temperature, reacts in the contact window to form what is commonly called a "silicide". Silicides are well known in the art and provide dependable silicon contact as well as low ohmic resistance.
Silicides have gained in popularity due to the shrinking dimensions of the contact window. As the contact window decreases, it is important that contact resistance remain relatively low. For that reason, silicides remain a mainstay in semiconductor processing. However, as device dimensions shrink, so does the spacing between contact windows. Any lateral migration of silicide occurring between closely spaced contact windows must be carefully monitored and controlled. Otherwise, a phenomenon often referred to as "silicide shorting" can occur.
Silicide shorting often arises when the refractory metal is titanium, and where titanium silicide is allowed to form between silicon contact windows, wherein the silicon comprises, e.g., a polysilicon gate and/or a silicon source/drain area. In a lightly doped drain (LDD) process, a sidewall spacer normally exists in the region between the polysilicon gate and source/drain areas. The sidewall spacer is fairly small in size and can allow titanium silicide formation over a portion of or the entire spacer thereby providing a capacitive-coupled or fully conductive path between the polysilicon gate and the source/drain region. See, e.g., Miller, "Titanium Silicide Formation by RTA: Device Implications", First International RTP Conference, (RTP, 1993) Sep. 8-10, 1993.
FIG. 1 is provided to better understand the phenomenon of silicide shorting as it pertains to LDD technology. FIG. 1 illustrates a cross-sectional view along plane A--A of FIG. 2, wherein an MOS device 10 is shown having a pair of source/drain regions 12, a polysilicon gate 14 and pair of sidewall spacers 16, all of which are formed between field oxide areas 18. FIG. 1 illustrates a MOS processing methodology occurring after silicide formation but before the patterning of overlying interconnect. Silicide 20 is formed in the contact windows between the interconnect (not shown) and underlying silicon (i.e., source/drain silicon regions 12 and gate polysilicon 14). Silicide 20 can be fairly thin, similar to gate oxide 22. When formed, silicon underneath silicide 20 (i.e., silicon from threshold adjust implant area 24, LDD implant 26, and/or source/drain implant 28 of substrate 30) can, when heated, diffuse into the refractory metal and react therewith. The reacted metal silicide regions 20 remain after etch, as shown. Refractory metal can, in some instances, react with silicon in the SiO.sub.2 sidewall spacer or can migrate along spacer 16 between source/drain 12 and polysilicon 14 to form unwanted silicide 20 over spacer 16. Silicide upon spacer 16 can, over time, creep toward one another in the direction indicated by the arrows. Eventual corrosion-induced connection or shorting of silicide 20 over spacer 16 may occur thereby presenting a device reliability problem. Corrosion-induced shorting or "silicide shorting" may be caused by moisture leaking into the integrated circuit, underneath the passivation layer. It is postulated that the moisture provides electrolysis along electric current flow path thereby bridging contaminant materials along the path and between adjacent silicides 20 overlying spacer 16.
In an effort to overcome silicide shorting problems, many researchers advocate a multiple step process. First, a refractory metal such as titanium is deposited over the entire wafer. Next, the metal film is heated to a low temperature in the presence of a nitrogen ambient in order to form a reacted, relatively high-resistance silicide in the contact windows. Next, the unreacted metal is removed using a wet chemical etch (e.g., NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O) thereby leaving reacted metal or metal silicide in the contact windows. Finally, a higher temperature anneal is performed in order to produce a lower resistivity silicide. Two anneal steps are necessary in order to prevent unwanted or excessive silicide formation which would occur if the first anneal temperature is comparable to the second (highest) anneal temperature. Thus, first anneal must be maintained at a maximum temperature of approximately 600.degree.-700.degree. C., while the subsequent anneal can extend up to approximately 800.degree. C.
The introduction of nitrogen into the first anneal process step is important in order for the nitrogen to diffuse into the metal and effectively nitrate the upper surface of the metal during the same time in which the lower surface of the metal forms silicide. It is possible that the anneal temperature can be excessive and nitrogen incorporation/nitridation can be minimal. Absent nitrogen atoms, which are used to compete with the titanium-silicon bonds forming in the silicide, complete silicidation of the metal can occur.
Not only is it important to carefully control the amount of silicidation as well as nitridation, and to strike a balance between the two, but it is also important to minimize exposure of the refractory metal to oxygen during silicide formation. In the two step anneal process described above, after the first anneal is completed within an RTA chamber, the silicon substrate is removed from the chamber and subjected to a wet etch. Withdrawal of the substrate from the chamber allows native oxides or other impurities to grow or deposit upon the reacted metal silicide. The native oxides or impurities cannot, in all instances, be removed by wet etch thereby leaving deleterious amounts of oxides and impurities in the contact window. It is well known that oxides in the contact window can, inter alia, impede or substantially reduce conductivity within the contact window.
A still further problem with the two step anneal process described above is the need to carefully monitor first anneal temperatures. If first anneal temperatures exceed a specified amount, then excessive silicidation can occur in the contact area with minimum simultaneous nitridation. However, when the contact window comprises a heavy doped source/drain region, it is oftentimes necessary to increase silicidation temperature given the relative absence of silicon (in proportion to impurity atoms) within the source/drain. Higher temperature anneal necessary to effectuate silicidation in the heavy doped source/drain contact windows may increase silicidation in the source/drains but lead to excessive silicidation in other contact regions, such as a lightly doped polysilicon, where silicon atoms are plentiful.